1. Field of the Invention
The present invention relates to a multilayer ceramic electronic component, a multilayer ceramic substrate, and a method for manufacturing a multilayer ceramic electronic component.
2. Description of the Related Art
In recent years, the performance of electronic components in the electronics field has been significantly improved, thereby contributing to speeding up of information processing, miniaturization, and diversification of function of information processing apparatuses such as a large scale computer, a mobile communication terminal, a personal computer, and other apparatuses.
One such electronic component is a multichip module (MCM) in which a plurality of semiconductor devices, such as VLSI and ULSI, is mounted on a ceramic substrate. Such a module includes a ceramic multilayer substrate in which wiring conductors are three-dimensionally arranged to increase the mounting density of LSIs and securely electrically connecting LSIs.
The ceramic multilayer substrate is formed by stacking a plurality of ceramic layers and is provided with wiring conductors for forming circuits on a surface of the substrate and inside the substrate. Mobile communication terminals, such as a cellular phone and an automobile radio communication device, must have highly functional, high-density mounting, and further miniaturization is required. In addition, depending on the application, products using the multilayer ceramic substrate must be resistant to impact.
On the other hand, as a method for mounting a semiconductor device on a substrate, a mounting method has been proposed in which as shown in FIG. 11, solder balls 54 provided on a semiconductor element 53 are melt-bonded to a conductor pattern (bump) 52 provided on a substrate 51 using via electrodes or printed electrodes, and a thermosetting resin 55 is provided to form an impact-relaxing layer between the substrate 51 and the semiconductor element 53 in order to improve impact resistance (see, for example, Japanese Unexamined Utility Model Registration Application Publication No. 4-99834).
Such a mounting method or mounting structure is effective to improve impact resistance of a product using a ceramic multilayer substrate. However, when such a mounting structure is used, in order to miniaturize a product, it is necessary to further decrease the size of the solder balls 54 and the gap between the solder balls.
However, when the diameter of the solder balls is decreased, the electrode bonding area (bump area) for securing conductivity is decreased, and the thickness of the thermosetting resin (impact-relaxing layer) 55 provided between the substrate 51 and the semiconductor element 53 is decreased, such that the impact resistance is insufficient even using a ceramic multilayer substrate having such a mounting structure as disclosed in Japanese Unexamined Utility Model Registration Application Publication No. 4-99834).
In addition, a conventional mounting structure (semiconductor device) is shown in FIG. 12 in which electrodes 62 provided on the rear surface of a semiconductor element 61 are mounted on a multilayer wiring substrate 64 having a plurality of projecting electrodes 63 which are provided on a surface thereof and which have conductive adhesive ends leveled to the same plane, the electrodes 62 of the semiconductor element 61 and the ends of the projecting electrodes 63 are electrically bonded, and a shrinkable insulating resin layer 65 is filled between the semiconductor element 61 and the multilayer wiring board 64 (see, for example, Japanese Unexamined Patent Application Publication No. 11-26631).
In a semiconductor device including the semiconductor element 61 mounted on the multilayer wiring substrate 64, the mounting structure of Japanese Unexamined Patent Application Publication No. 11-26631 permits mounting of the semiconductor element 61 with high reliability and no requirement for the multilayer wiring substrate 64 to be extremely flat.
However, in the conventional mounting structure, limits actually occur on a reduction in diameter of the projecting electrodes (columnar electrodes) 63, improvement in the aspect ratio, i.e., the ratio (height/diameter) of the height to the diameter of the projecting electrodes (columnar electrodes) 63, and a reduction in the gap between the adjacent projecting electrodes (columnar electrodes) 63, thereby failing to sufficiently comply with the requirement for the projecting electrodes (columnar electrodes) 63 to have a smaller diameter and a higher aspect ratio.